Operation-centric Hardware Description and Synthesis Operation-centric Hardware Description and Synthesis

In an operation centric framework the behavior of a system is decomposed and de scribed as a collection of operations An operation is de ned by a predicate condition and an e ect on the system s state An execution of the system corresponds to some sequential interleaving of the operations such that each operation in the sequence pro duces a state that enables the next operation An operation s e ect on the system is global and atomic In other words an operation reads the state of the system in one step and if enabled the operation updates the state in the same step This atomic semantics simpli es the task of hardware description by permitting the designer to formulate each operation as if the system were otherwise static This thesis develops a method for hardware synthesis from an operation centric description The crux of the synthesis problem is in nding a synchronous state tran sition system that carries out multiple parallelizable operations per clock cycle and yet maintains a behavior that is consistent with the atomic and sequential semantics of the operations The thesis rst de nes an Abstract Transition System ATS an operation centric state machine abstraction The thesis next develops the theories and algorithms to synthesize an e cient synchronous digital circuit implementation of an ATS Finally the thesis presents TRSpec a source level operation centric hardware description language based on the formalism of Term Rewriting Systems The results of this thesis show that an operation centric framework o ers a sig ni cant improvement over traditional hardware design ows The TRSpec language and synthesis algorithms developed in this thesis have been realized in the Term Rewriting Architectural Compiler TRAC This thesis presents the results of several operation centric design exercises using TRSpec and TRAC In an example based on a bit MIPS integer core the operation centric description can be developed ve times faster than a hand coded structural Verilog description Nevertheless the circuit implementation produced by the operation centric framework is comparable to the hand coded design in terms of speed and area Thesis Supervisor Arvind Title Johnson Professor of Computer Science and Engineering